Ðþí   —   H  è   (            ¯       €                                           RTSM_VE_AEMv8A            arm,rtsm_ve,aemv8a arm,vexpress                      "            1      clk24mhz             fixed-clock          =             Jn6          Zv2m:clk24mhz             m         refclk1mhz           fixed-clock          =             J B@         Zv2m:refclk1mhz           m         refclk32khz          fixed-clock          =             J  €          Zv2m:refclk32khz          m         v2m-3v3          regulator-fixed          u3V3          „ 2Z          œ 2Z           ´         m         mcc          arm,vexpress,config-bus          È      oscclk1          arm,vexpress-osc             ã               üjepÈîà         =             Zv2m:oscclk1          m         reset            arm,vexpress-reset           ã             muxfpga          arm,vexpress-muxfpga             ã             shutdown             arm,vexpress-shutdown            ã             reboot           arm,vexpress-reboot          ã   	          dvimode          arm,vexpress-dvimode             ã                bus@8000000          simple-bus           "            1         x                                                                                                                                       ?     ´  2                                                                                                                                                                                                                                     	          	              
          
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                !          !              "          "              #          #              $          $              %          %              &          &              '          '              (          (              )          )              *          *      motherboard-bus         @rs1          arm,vexpress,v2m-p1 simple-bus           "            1                          flash@0          arm,vexpress-flash cfi-flash            S                             W         ethernet@202000000           smsc,lan91c111          S                 b         iofpga-bus@300000000             simple-bus           "            1                             sysreg@10000             arm,vexpress-sysreg         S               m        }            m         sysctl@20000             arm,sp810 arm,primecell         S              ‰                 �refclk timclk apb_pclk           =         0   Ztimerclken0 timerclken1 timerclken2 timerclken3          œ                                 ¬                     m         aaci@40000           arm,pl041 arm,primecell         S              b           ‰         	  �apb_pclk          mmci@50000           arm,pl180 arm,primecell         S              b   	   
        Ã                   Ì                  Õ ·         ã           ‰              �mclk apb_pclk         kmi@60000            arm,pl050 arm,primecell         S              b           ‰              �KMIREFCLK apb_pclk        kmi@70000            arm,pl050 arm,primecell         S              b           ‰              �KMIREFCLK apb_pclk        serial@90000             arm,pl011 arm,primecell         S 	             b           ‰              �uartclk apb_pclk          serial@a0000             arm,pl011 arm,primecell         S 
             b           ‰              �uartclk apb_pclk          serial@b0000             arm,pl011 arm,primecell         S              b           ‰              �uartclk apb_pclk          serial@c0000             arm,pl011 arm,primecell         S              b           ‰              �uartclk apb_pclk          wdt@f0000            arm,sp805 arm,primecell         S              b            ‰              �wdog_clk apb_pclk         timer@110000             arm,sp804 arm,primecell         S              b           ‰                        �timclken1 timclken2 apb_pclk          timer@120000             arm,sp804 arm,primecell         S              b           ‰                       �timclken1 timclken2 apb_pclk          virtio-block@130000          virtio,mmio         S              b   *      rtc@170000           arm,pl031 arm,primecell         S              b           ‰         	  �apb_pclk          clcd@1f0000          arm,pl111 arm,primecell         S            	  ïcombined            b           ‰              �clcdclk apb_pclk            ÿ   	   port       endpoint               
                           m                        chosen        aliases       ?  7/bus@8000000/motherboard-bus/iofpga-bus@300000000/serial@90000        ?  ?/bus@8000000/motherboard-bus/iofpga-bus@300000000/serial@a0000        ?  G/bus@8000000/motherboard-bus/iofpga-bus@300000000/serial@b0000        ?  O/bus@8000000/motherboard-bus/iofpga-bus@300000000/serial@c0000        cpus             "            1       cpu@0           Wcpu       
   arm,armv8           S                cspin-table          q    € ÿø        ‚         cpu@1           Wcpu       
   arm,armv8           S               cspin-table          q    € ÿø        ‚         cpu@2           Wcpu       
   arm,armv8           S               cspin-table          q    € ÿø        ‚         cpu@3           Wcpu       
   arm,armv8           S               cspin-table          q    € ÿø        ‚         l2-cache0            cache            m            memory@80000000         Wmemory           S    €       €      €       €         reserved-memory          "            1               vram@18000000            shared-dma-pool         S            €           “         m   	         interrupt-controller@2c001000            arm,gic-400 arm,cortex-a15-gic                      "             š      @  S    ,             ,               , @             , `                 b      	           m         timer            arm,armv8-timer       0  b                              
           Jõá       pmu          arm,armv8-pmuv3       0  b       <          =          >          ?         panel            arm,rtsm-display       port       endpoint                        m   
               	model compatible interrupt-parent #address-cells #size-cells #clock-cells clock-frequency clock-output-names phandle regulator-name regulator-min-microvolt regulator-max-microvolt regulator-always-on arm,vexpress,config-bridge arm,vexpress-sysreg,func freq-range ranges #interrupt-cells interrupt-map-mask interrupt-map arm,v2m-memory-map reg bank-width interrupts gpio-controller #gpio-cells clocks clock-names assigned-clocks assigned-clock-parents cd-gpios wp-gpios max-frequency vmmc-supply interrupt-names memory-region remote-endpoint arm,pl11x,tft-r0g0b0-pads serial0 serial1 serial2 serial3 device_type enable-method cpu-release-addr next-level-cache no-map interrupt-controller 